The ARM system designed here is used to perform movie superposition. It is a system based on ARM processor, HES board and PLI interface.
Hardware: HES board 2000, ARM daughter board. Software: Active-HDL, ARM Device Suite, DVM, ISE... more...
The ASFTest tool allows designers to automatically prepare testbenches for projects of state machines. There are up to three strategies of testbench testing that can be set individually for specific needs in users' projects. This tool feature has been implemented to speed up the verification process of design units described by means of the state machine diagram... more...
The Sigetest fault simulation system allows designers to simulate test sequences and analyze fault coverage and test quality for complex digital devices. Sigetest supports output of modern synthesis tools (Synplicity® Synplify, Synopsys® Design Compiler) in form of VHDL gate-level net lists. Verilog design entry for Sigetest is in development... more...
The CoolDOC Product is a solution for documenting the source code and semantic dependencies of complex software systems. It is designed to give development teams and single developers the tool they need to catch the project internal problems on early stages, starting at the low-level small mistakes to architectural drawbacks... more...
For implementation proposed net model which executes Russian language adjective analysis. Net allows defining other properties of word based on defined properties. VHDL language is used for formal description of specification and design development. Model represented as net: nodes are sets of word attribute values, arcs are relations between them... more...
Video stream processing ARM based System-on-Chip (SoC)
The ASFTest tool allows designers to automatically prepare testbenches for projects of state machines. There are up to three strategies of testbench testing that can be set individually for specific needs in users' projects. This tool feature has been implemented to speed up the verification process of design units described by means of the state machine diagram... 
The Sigetest fault simulation system allows designers to simulate test sequences and analyze fault coverage and test quality for complex digital devices. Sigetest supports output of modern synthesis tools (Synplicity® Synplify, Synopsys® Design Compiler) in form of VHDL gate-level net lists. Verilog design entry for Sigetest is in development... 
The CoolDOC Product is a solution for documenting the source code and semantic dependencies of complex software systems. It is designed to give development teams and single developers the tool they need to catch the project internal problems on early stages, starting at the low-level small mistakes to architectural drawbacks... 
For implementation proposed net model which executes Russian language adjective analysis. Net allows defining other properties of word based on defined properties. VHDL language is used for formal description of specification and design development. Model represented as net: nodes are sets of word attribute values, arcs are relations between them...